Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetic elements. For example, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM).
Referring to FIG. 1, a diagram of a conventional STT-MRAM cell 100 is illustrated. The STT-MRAM bit cell 100 includes magnetic tunnel junction (MTJ) storage element 105, transistor 110, bit line 120 and word line 130. The MTJ storage element is formed, for example, from a pinned layer and a free layer, each of which can hold a magnetic field, separated by an insulating (tunnel barrier) layer as illustrated in FIG. 1. The STT-MRAM bit cell 100 also includes a source line 140, sense amplifier 150, read/write circuitry 160 and bit line reference 170. Those skilled in the art will appreciate the operation and construction of the memory cell 100 is known in the art. Additional details are provided, for example, in M. Hosomi, et al., A Novel Nonvolatile Memory with Spin Transfer Torque Magnetoresistive Magnetization Switching: Spin-RAM, proceedings of IEDM conference (2005), which is incorporated herein by reference in its entirety.
Referring to FIG. 2, in conventional designs, the source lines (SL) of the magnetic tunnel junction (MTJ) bit cell arrays are arranged to be parallel to either the bit line (BL) or the word line. However, in conventional designs there is no direct and parallel overlap between the source line (SL) and bit line (BL) due to via and metal spacing rules. Therefore, the minimum bit cell size of conventional designs cannot be reduced or minimized as a result of metal and via spacing rules.
FIG. 3 is a top down screen view of a conventional magnetic tunnel junction (MTJ) bit cell array having source lines (SL) arranged parallel to the bit lines (BL). As shown in FIG. 3, the source lines (SL) do not overlap the bit lines (BL), and thus, the bit cell size is limited by the spacing rules between the source lines (SL) and the bit lines (BL).